This invention relates to electro-static-discharge (ESD) protection circuits, and more particularly to cascaded-transistor input-protection devices.
Relatively small electric shocks can melt or otherwise destroy tiny structures in an integrated circuit (IC). To reduce such damage, input and output pads of IC chips are typically connected to protection devices specifically designed to shunt electro-static-discharges (ESD). These ESD-protection devices have been effective for semiconductor processes used in the last decade.
Processing improvements have continued to reduce the size of IC transistors and the thicknesses of films used to make the transistors. For example, the gate oxide between the silicon substrate and the polysilicon or other gate material has been reduced to as little as 32 angstroms for a process with a minimum gate length of 0.18 micron. These thin gate oxides present a challenge since they may be damaged by relatively small voltages.
For example, a gate oxide may have a breakdown of 4 volts, which is less that the traditional 5-volt power supply. Reduced power-supply voltages of 3 or 1.8 volts have helped prevent oxide breakdown. However, the IC chip with the thin gate oxide may be electrically connected to another chip that drives S-volt signals that could destroy the delicate gate oxides. Even reduced voltages such as 3.3 volts may damage gate oxides with breakdown voltages of 4 volts, since a 3.3-volt signal is so close to the breakdown limit. The long-term reliability of the gate oxide is also a concern.
Some dual-gate-oxide processes allow for a thin gate oxide to be used for core transistors, but a thicker gate oxide to be used for I/O transistors. While useful, the extra processing steps for the thicker I/O oxide add cost and are not desirable.
Semiconductor processes with low gate-breakdown voltages may require cascading transistors to reduce the voltage applied to any single transistor. Stacked or cascaded transistors are widely used for I/O circuits when only thin gate oxides are available. FIG. 1 shows an output buffer using cascaded transistors. Internal circuitry including a pre-driver generate signal VN to the gate of n-channel driver transistor 16. A bias voltage VBN is applied to the gate of n-channel limiting transistor 14.
The bias voltage VBN can be a constant voltage (such as Vcc) that causes limiting transistor 14 to remain on. The voltage stress seen by the gate oxide at the Drain/Gate overlap region of transistor 14 is reduced to Vpad Vcc, which is less than the gate oxide breakdown voltage.
When a high and potentially damaging voltage is applied to the pad, this voltage is reduced somewhat by the voltage drop across the channel of limiting transistor 14. Thus the voltage on node NIN is less that the maximum voltage applied to the pad, reducing the gate-to-drain voltage on driver transistor 16 to Vcc-Vtn.
Also, since the bias voltage VBN may be set to power (Vcc), the gate-to-drain voltage of limiting transistor 14 can be less than the maximum that could occur if its gate was driven fully to ground. Thus the voltage across the gate of limiting transistor 14 is less than the gate breakdown voltage.
FIG. 2 shows that n-channel cascaded transistors in an output buffer are often laid out parallel to one another. Polysilicon gates are laid out vertically across an active region in the p-type substrate, with sources and drain between the poly gates in the active areas. Contacts to metal layers can be included in these source and drain regions but are not shown.
In this example, the source active region which is connected to ground is to the left of the poly gate of n-channel driver transistor 16, while the drain region is to the right of the poly gate of transistor 16. The active area for the drain of transistor 16 is shared with the source of limiting transistor 14, saving die area. This source/drain region is node NIN. This region may be made narrower that for the ground and pad connections since metal contacts may not be needed for this intermediate node.
N-channel limiting transistor 14 has its source on the left, node NIN, and its drain on the right, pad node PAD. Often several legs or fingers of polysilicon gates are required to meet the desired gate width of the overall transistor. Thus a second polysilicon gate transistor 14′ for transistor 14 is to the right, sharing pad node PAD and having a source node NIN′ to the right. Nodes NIN and NIN′ may or may not be connected together by metal lines and contacts.
FIG. 3 shows a cross-section of the n-channel cascaded transistors laid out in FIG. 2. N+ source and drain regions are connected to ground, node NIN, the pad, and node NIN′ from left to right, while poly gates are formed above channels in the substrate for transistors 16, 14, 14′.
Parasitic lateral NPN transistors are also formed by the MOS transistor structures. For example, the grounded source and drain at node NIN of transistor 16 form one NPN transistor, while the source at node NIN and drain at node PAD of transistor 14 form another NPN transistor. The bases of these transistors are the channels in the p-substrate under the poly gates.
A third lateral NPN transistor 22 is shown. This lateral NPN transistor is larger, spanning two transistors 16, 14. The emitter of NPN transistor 22 is the grounded source of driver transistor 16, while the collector of NPN transistor 22 is the drain of limiting transistor 14 which is connected to the pad. The base of NPN transistor 22 is the p-type substrate between the ground and pad N+ regions.
This NPN transistor 22 goes under the intermediate N+ region of node NIN, and current flows under this intermediate NPN region when NPN transistor 22 is turned on, such as during an ESD event.
The base width of this larger NPN transistor 22 is much larger than the base width of the smaller parasitic NPN transistors that correspond to transistors 16, 14. Thus NPN transistor 22 is less likely to conduct given identical bias conditions of emitter, base, and collector terminals of the parasitic NPN transistors.
However, when two n-channel transistors are cascaded, the bias conditions are not identical but are very different. The intermediate node NIN is not biased but is floating. The snapback characteristics of this n-channel stack structure has been theoretically explained in James Miller's paper “Engineering the Cascoded NMOS Output Buffer for Maximum Vt1” published in the 2000 EOS-ESD Symposium Technical Digest, pp.308-317. Empirical measurements have shown that the n-channel cascaded/stack configuration has a higher trigger voltage Vt1 and a higher snapback holding voltage Vsb, but a lower secondary breakdown current It2 as compared to a single n-channel transistor. This means a degraded ESD performance is expected in a stacked transistor structure.
Earlier output buffers that did not cascade transistors had just the smaller parasitic NPN transistor. This smaller NPN transistor was easier to turn on during an ESD event since it had a smaller base width. Thus the MOS driver transistors of earlier output buffers served as a good ESD protection device due to their parasitic NPN transistors.
The higher breakdown voltage of the larger NPN transistor 22 is undesirable since it allows a larger voltage to occur on the pad during an ESD event. The larger ESD voltage that occurs before the parasitic NPN transistor turns on can damage the transistors and gate oxides, causing permanent failures from ESD events.
Simply adding a standard ESD structure to the pad can cause reliability failures. A standard ESD structure with a single transistor to shunt current from the pad to ground or power could have gate-oxide failures due to the full voltage across the one shunt transistor. The width of the base of NPN transistor 22 could be reduced by removing any contacts to metal in the shared source/drain region (node NIN), but then this layout is no longer generic and useable for other logic gates that need the contacts.
A new ESD device based on a silicon-controlled rectifier (SCR) has been developed by one of the inventors. Ming-Dour Ker published the article “Electrostatic Discharge Protection Design for Mixed-Voltage CMOS I/O Buffers” in IEEE Journal of Solid State Circuits, vol.37 #8 pp.1046-1055, August,2002. The Stacked-NMOS Triggered SCR device (SNTSCR) is disclosed. The SNTSCR device requires synchronized triggering of the gates of the Stacked-NMOS transistors embedded in the new SCR device.
What is desired is a cascaded ESD-protection structure that can use the cascaded transistors of an output buffer. Cascaded transistors are desired to reduced voltages applied across thin gate oxides of the transistors. A modification to a cascaded output buffer is desired to reduce the breakdown or snap-back voltage. A more robust ESD structure with a lower breakdown voltage is desired to protect the delicate transistors and gate oxides of smaller devices. Use of the new stacked-NMOS-triggered SCR in a cascaded-transistor output is desired.